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| PMC-Sierra,Inc. PM7324 S/UNI-ATLAS compliant, per-VC programmable dual leaky bucket policing with a programmable action (tag, discard, or count only) for each bucket, each with 3 programmable 16 bit non-compliant cell counts. * Per-PHY single leaky bucket policing with a programmable action (tag, discard, or count only) * Guaranteed Frame Rate (GFR) Policing with Minimum Cell Rate Frame Tagging. * Per-PHY counts include CLP0 cells, CLP1 cells, OAM cells, errored OAM cells, unassigned/invalid cells and policing violations. * Per-device counts include total cells received/transmitted, and physical layer cells. SATURN User Network Interface ATM Layer Solution FEATURES * Monolithic single chip device which handles bi-directional ATM Layer functions including VPI/VCI address translation, cell appending, policing (ingress only), cell counting and OAM requirements for 65536 VCs (virtual connections). * Instantaneous bi-directional transfer rate of 800 Mbit/s supports a bidirectional cell transfer rate of 1.42x106 cells/s. * Ingress input interface supports an 8 or 16 bit PHY interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2). * Ingress output interface supports an 8 or 16 bit SCI-PHY (52 - 64 byte cell) interface (Utopia Level 1) to a switch fabric. * Egress input and output interfaces support an 8 or 16 bit SCI-PHY (52 64 byte cell) interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2). * Compatible with a wide range of switching fabrics and traffic management architectures. * Ingress functionality includes a highly flexible search engine that covers the entire PHYID/VPI/VCI address range, dual leaky bucket policing, per-VC cell counts, OAM-FM and OAM-PM processing. * Egress functionality includes direct address lookup, per-VC cell counts, OAM-FM and OAM-PM processing. Per-PHY output buffering scheme resolves the head-of-line blocking issue. * Includes a FIFO buffered 16-bit microprocessor bus interface for cell insertion and extraction, deterministic VC Table access, status monitoring and configuration of the device. * Supports DMA access for cell extraction. * The UTOPIA and external SRAM interfaces are 52 MHz max. PACKAGING * Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. * Implemented in low power, 0.35 micron, 3.3 Volt CMOS technology with 5 Volt tolerant and microprocessor interface, 3.3V UTOPIA and external synchronous SRAM interfaces. * Packaged in 432 pin ball grid array (BGA) package. OAM * ITU-I.610 compliant OAM on both Ingress and Egress directions. * Complete Fault Management (AIS, RDI, CC) processing, for VP/VC, Segment/End-to-end flows on all VC's. * Complete Performance Monitoring processing, for VP/VC, Segment/Endto-end, Forward/Backward flows, on 256 Bi-directional VC's. APPLICATIONS * WAN ATM Core and Edge Switches * ATM Enterprise and Workgroup Switches * Access Switches/Multiplexers CELL COUNTING * Per-VC counts include CLP0 cells, CLP1 cells, policing violations. BLOCK DIAGRAM To External Synchronous SRAM ISD[63:0] ISP[7:0] ISA[19:0] ISRWB ISOEB ISADSB ISYSCLK SCI-PHY Level1 Interface (Slave) Ingress Output Cell Interface ODAT[15:0] OPRTY OSOC OFCLK OCA ORDENB OTSEN IDAT[15:0] IPRTY IFCLK ISOC ICA[1] IWRENB[1] IAVALID/ICA[4] IADDR[4:3]/ICA[3:2] IADDR[2:0]/IWRENB[4:2] IPOLL SCI-PHY Level1/ Level2 Interface (Slave) ESD[31:0] ESP[3:0] ESA[19:0] ESADSB ESRWB ESOEB ESYSCLK SCI-PHY Level1/ Level2 Interface (Master) RDAT[15:0] RPRTY RRDENB[1] RCA[1] RADDR[4:3]/RCA[3:2] RAVALID/RCA[4] ADDR[2:0]/RRDENB[4:2] RSOC RFCLK RPOLL TDAT[15:0] TPRTY TWRENB[1] TCA[1] TADDR[4:3]/TCA[3:2] TAVALID/TCA[4] TADDR[2:0]/TWRENB[4:2] TSOC TFCLK TPOLL SCI-PHY Level1/ Level2 Interface (Master) Ingress Search Engine Ingress Input Cell Interface Ingress Cell Processor Ingress Backward Cell Interface PHY Statistics Collection Egress Backward Cell Interface Egress Output Cell Interface Egress Cell Processor Egress Input Cell Interface Ingress Microprocessor Cell Interface Egress Microprocessor Cell Interface JTAG Interface Microprocessor Interface POLICING * ITU-I.371, ATM Forum TM4.0 To External Synchronous SRAM PMC-980489 (R2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT'S CUSTOMERS' INTERNAL USE (c) 1999 PMC-Sierra, Inc. PM7324 S/UNI-ATLAS SATURN User Network Interface ATM Layer Solution TYPICAL APPLICATIONS S/UNI-ATLAS OC-12 PORT CARD APPLICATION Physical Layer ATM Layer Traffic Management OC-12 Optics PM5356 S/UNI-622-MAX PM7324 S/UNI-ATLAS PM73487 QRT S/UNI-ATLAS QUAD OC-3 PORT CARD APPLICATION Physical Layer ATM Layer Traffic Management OC-3 Optics OC-3 Optics OC-3 Optics OC-3 Optics PM5349 S/UNI-QUAD PM7324 S/UNI-ATLAS PM73487 QRT Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-980489 (R2) (c) 1999 PMC-Sierra, Inc. August, 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT'S CUSTOMERS' INTERNAL USE |
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